View FMP1617DAX_7905482.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

FMP1617DAX cmos lpram revision 0.4 jul. 2010 1 document title 1m x 16 bit super low power and low voltage full cmos ram revision history final jul. 21 st , 2010 removed page write operation 0.4 revision no. history draft date remark 0.0 initial draft dec,08 th , 2008 preliminary 0.1 revised load condition revised i/o power (1.7v to vcc ? 2.7v to vcc) revised vih (vcc-0.4 ? 0.8vccq) revised vil (0.4 ? 0.2vccq) jul. 3 rd , 2009 preliminary 0.2 revised isb1 (110ua ? 100ua) revised isb0c (110ua ? 100ua) revised isb0b (100ua ? 80ua) revised isb0a (90ua ? 70ua) nov. 25 th , 2009 preliminary 0.3 correct typo in array refresh area of mode register set feb. 3 rd , 2010 preliminary
FMP1617DAX cmos lpram revision 0.4 jul. 2010 2 1m x 16 bit super low power an d low voltage full cmos ram pin description 1 2 3 4 5 6 a b c d e f g h /lb /oe a0 a1 a2 i/o9 /ub a3 a4 /cs i/o10 i/o11 a5 a6 i/o2 vss i/o12 a17 a7 i/o4 vccq i/o13 dnu a16 i/o5 i/o15 i/o14 a14 a15 i/o6 i/o16 a19 a12 a13 we a18 a8 a9 a10 a11 /zz i/o1 i/o3 vcc vss i/o7 i/o8 nc 48-fbga : top view(ball down) name function name function /zz low power modes vcc core power /cs chip select input vccq i/o power /oe output enable input vss ground /we write enable input /ub upper byte(i/o9~16) a0~a19 address inputs /lb lower byte(i/o 1~8) i/o1~i/o16 data inputs/outputs dnu do not use functional block diagram precharge circuit. clk gen. vcc vss memory array row addresses i/o circuit column select data cont data cont column addresses data cont control logic /cs /oe /we /ub /lb /zz i/o9~i/o16 i/o1~i/o8 row select product family product family operating voltage (v) speed power dissipation icc1 icc2 isb1 (cmos standby current) min. typ. max. f = 1mhz f = fmax typ. max. typ. max. typ. max. FMP1617DAX- h 60 e FMP1617DAX- h 70 e 2.7 3.0 3.3 60ns 70ns 1.5ma 3ma 15ma 12ma 20ma 70ua 100ua 1. typical values are included for reference only and are not guar anteed or tested. typical values are measured at vcc = vcc (ty p) and t a = 25c. 2. h =fbga(pb-free & halogen free), w =wafer 3. operating temperature range: s (-10?c~60?c), c (0?c~70?c), e (-25?c~85?c), i (-40?c~85?c) features ? process technology : full cmos ? organization : 1m x 16 ? power supply voltage : 2.7~3.3v ? three state output and ttl compatible ? separated i/o power(vccq) & core power(vcc) ? operating temperature ranges: special (-10?c to +60?c) commercial (0?c to +70?c) extended (-25?c to +85?c) industrial (-40?c to +85?c) ?package type : 48-fbga-6.00x8.00 mm 2 FMP1617DAX-hxxx : pb-free & halogen free ? low power & page modes fmp1617da1 : support the pasr/dpd function fmp1617da2 : support the direct dpd function fmp1617da4 : support the pasr/dpd/page function fmp1617da5 : support the direct dpd/page function ? page read/write operation by 16 words (fmp1617da4, fmp1617da5) ? dpd mode by using mrs only (fmp1617da1, fmp1617da4) ? direct dpd mode when /zz goes low (fmp1617da2, fmp1617da5)
FMP1617DAX cmos lpram revision 0.4 jul. 2010 3 product list part name function FMP1617DAX- h 60 e FMP1617DAX- h 70 e 60ns, vcc=3.0v, vccq=3.0v 70ns, vcc=3.0v, vccq=3.0v functional description /cs /zz /oe /we /lb /ub i/o1-8 i/o9-16 mode power hhx 1) x 1) x 1) x 1) high-z high-z deselected standby x 1) lx 1) x 1) x 1) x 1) high-z high-z deselected direct dpd 2) hlx 1) x 1) x 1) x 1) high-z high-z deselected low power modes 3) x 1) hx 1) x 1) h h high-z high-z deselected standby l hhhlx 1) high-z high-z output disabled active hhhx 1) l high-z high-z output disabled active lh lh l h dout high-z lower byte read active h l high-z dout upper byte read active l l dout dout word read active x 1) l l h din high-z lower byte write active h l high-z din upper byte write active l l din din word write active 1. x means don?t care.(must be low or high state) 2. in case of fmp1617da2 & fmp1617da5 product 3. in case of fmp1617da1 & fmp1617da4 product 1. h =fbga(pb-free & halogen free), w =wafer 2. operating temperature range: s (-10?c~60?c), c (0?c~70?c), e (-25?c~85?c), i (-40?c~85?c) absolute maximum ratings 1) 1. stresses greater than those listed under ?absolute maximum ra tings? may cause permanent damage to the device. functional ope ration should be restricted to recommended operating condition. exposure to absolute maximum rati ng conditions for extended periods may affect reliability. recommended dc operating conditions note : 1. overshoot : vcc+1.0v in case of pulse width 20ns. 2. undershoot : -1.0v in case of pulse width 20ns. 3. overshoot and undershoot are sampled, not 100% tested. item symbol ratings unit voltage on any pin relative to vss vin, vout -0.5 to vcc+0.3v v voltage on vcc supply relative to vss vcc -0.2 to 3.6 v power dissipation pd 1.0 w storage temperature tstg -65 to 150 ?c item symbol FMP1617DAX unit min typ max supply voltage vcc 2.7 3.0v 3.3 v i/o operating voltage (vccq vcc) vccq 2.7 3.0v 3.3 v ground vss 0 0 0 v input high voltage vih 0.8vccq vccq vcc+0.2 1) v input low voltage vil -0.2 2) 00.2vccqv
FMP1617DAX cmos lpram revision 0.4 jul. 2010 4 dc and operating characteristics 1. capacitance is sampled, not 100% tested. capacitance 1) (f=1mhz , t a =25?c) item symbol test condition min max unit input capacitance cin vin=0v - 8 pf input/output capacitance cio vio=0v - 8 pf item symbol test conditions min max unit input leakage current ili vin=vss to vcc -1 1 ua output leakage current ilo /cs=vih, /zz=vih, /oe=vih or /we=vil, vio=vss to vcc -1 1 ua average operating current icc1 cycle time=1us, 100%duty, iio=0ma, /cs 0.2v, /zz=vih, vin 0.2v or vin vcc-0.2v -3ma icc2 cycle time=min, iio=0ma, 100% duty, /cs=vi l, /zz=vih, vin=vil or vih -20ma output low voltage vol iol=0.5ma 0.2vccq v output high voltage voh ioh=-0.5ma 0.8vccq v standby current(ttl) isb /c s=vih, /zz=vih, other inputs=vih or vil - 0.3 ma standby current(cmos) isb1 /cs vcc-0.2v, /zz vcc-0.2v, other inputs=0~vcc - 100 ua low power modes isb0 /zz 0.2v, other inputs=0~vcc, no refresh(dpd) - 10 ua isb0a /zz 0.2v, other inputs=0~vcc, ? refresh area selection - 70 ua isb0b /zz 0.2v, other inputs=0~vcc, ? refresh area selection - 80 ua isb0c /zz 0.2v, other inputs=0~vcc, al l refresh area selection - 100 ua device range ambient temperature vcc vccq FMP1617DAX-xxxs special -10 to +60 2.7v to 3.3v 2.7v to vcc FMP1617DAX-xxxc commercial 0 to +70 FMP1617DAX-xxxe extended -25 to +85 FMP1617DAX-xxxi industrial -40 to +85 operating range ac input/output reference waveform note: 1. ac test inputs are driven at vccq for a logic 1 and vss fo r a logic 0. input rise and fall times (10% to 90%) < 1.6ns. 2. input timing begins at vccq/2. 3. output timing ends at vccq/2. ac output load circuit dut 50 ? 30pf test point vccq/2 test points vccq/2 3 vccq/2 2 vccq vss input 1 output
FMP1617DAX cmos lpram revision 0.4 jul. 2010 5 ac characteristics (v cc =2.7v~3.3v) parameter list symbol speed bins units 60ns 70ns min max min max read read cycle time trc 60 20k 70 20k ns address access time taa - 60 - 70 ns chip select to output tco - 60 - 70 ns output enable to valid output toe - 25 - 25 ns /ub, /lb access time tba - 60 - 70 ns chip select to low-z output tlz 10 - 10 - ns /ub, /lb enable to low-z output tblz 10 - 10 - ns output enable to low-z output tolz 5 - 5 - ns chip disable to high-z outputthz0505 ns /ub, /lb disable to high-z outputtbhz0505 ns output disable to high-z outputtohz0505 ns output hold from address change toh 5 - 5 - ns write write cycle time twc 60 20k 70 20k ns chip select to end of write tcw 50 - 60 - ns address set-up time tas 0 - 0 - ns address valid to end of write taw 50 - 60 - ns /ub, /lb valid to end of write tbw 50 - 60 - ns write pulse width twp 50 - 50 - ns write recovery time twr 0 - 0 - ns write to output high-z twhz0505 ns data to write time overlap tdw 20 - 20 - ns data hold from write time tdh 0 - 0 - ns end write to output low-z tow 5 - 5 - ns page page mode cycle time tpc 20 - 25 - ns page mode address access time tpaa - 20 - 25 ns maximum cycle time tmrc - 20k - 20k ns /cs high pulse width tcp 10 - 10 - ns 1. /cs high pulse width is defined by /cs or (/ub and /lb) because /ub & /lb can make standby mode when /ub=high and /lb=high.
FMP1617DAX cmos lpram revision 0.4 jul. 2010 6 power up sequence 1. apply power 2. maintain stable power for a minimum of 150us with /cs=/zz=v ih standby mode state machines standby mode characteristics mode memory cell data standby current(ua) wait time(us) standby valid 100 (isb1) 0 low power modes invalid 10 (isb0) 150 ? valid 70 (isb0a) 0 ? valid 80 (isb0b) 0 valid 100 (isb0c) 0 initial state standby mode active mode low power modes 1 (16m/8m/4m bits) power on /cs=vil, /zz=vih /ub or/and /lb=vil /cs=vih (or/and /ub=/lb=vih) /zz=vih /cs=/zz=vih /cs=vih, /zz=vil /cs=vil, /zz=vih /ub or/and /lb=vil low power modes 2 (data invalid) wait 150us /cs=vih, /zz=vil /cs=vih, /zz=vil /cs=vih /zz=vil /cs=vih, /zz=vih /cs=vil, /zz=vih /ub or/and /lb=vil
FMP1617DAX cmos lpram revision 0.4 jul. 2010 7 read cycle (2) (/zz=/we=v ih ) 1. thz and tohz are defined as the ti me at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. 2. at any given temperature and voltage condition, thz(max.) is less than tlz(min.) both for a given device and from device to device interconnection. 3. do not access device with cycle timing s horter than trc(twc) for continuous periods > 20us. address taa tco tba toe toh tolz tblz tlz data valid high-z thz tbhz tohz /cs /ub, /lb /oe data out trc read cycle (1) (address controlled,/cs=/oe=v il , /zz=/we=v ih , /ub or/and /lb=v il ) address data out trc previous data valid data valid taa toh 1. thz and tohz are defined as the ti me at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. 2. at any given temperature and voltage condition, thz(max.) is less than tlz(min.) both for a given device and from device to device interconnection. 3. do not access device with cycle timing s horter than trc(twc) for continuous periods > 20us. 4. in case page address skew is over 3ns, tpaa will be out of spec. page read cycle (/zz=/we=v ih , 16 words access) a0~a3 taa tco tba toe high-z thz tbhz tohz /cs /ub, /lb /oe data out trc a4~a19 toh tpc tpc tpc tpc tpc tpc tpc tpaa tpaa tpaa tpaa tpaa tpaa tpaa tlz tblz tolz data valid data valid data valid data valid data valid data valid data valid data valid tmrc
FMP1617DAX cmos lpram revision 0.4 jul. 2010 8 write cycle (2) (/cs controll ed, /zz=/we=v ih ) address /cs /ub, /lb /we data out twc twr(4) tbw twp(1) high-z high-z data valid tdw tdh data in tcw(2) tas(3) taw write cycle (3) (/ub, /lb controlled, /zz=v ih ) 1. a write occurs during the overlap (twp) of lo w /cs and /we. a write begins when /cs goes low and /we goes low with asserting /ub or /lb for single byte operation or simultaneou sly asserting /ub and /lb for double byte operation. a write ends at the earliest transition when /cs goes high and we goes high. the twp is measured from the beginning of write to the end of write. 2. tcw is measured from the /cs going low to end of write. 3. tas is measured from the address valid to the beginning of write. 4. twr is measured from the end of write to the address change. twr applied in case a write ends as /cs or /we going high. 5. do not access device with cycle timing s horter than trc(twc) for continuous periods > 20us. address /cs /ub, /lb /we data out twc twr(4) tbw twp(1) high-z high-z data valid tdw tdh data in tcw(2) taw tas(3) write cycle (1) (/we controlled, /zz=v ih ) address /cs /ub, /lb /we data out twc tcw(2) twr(4) taw tbw twp(1) tas(3) high-z high-z data undefined data valid tdw tdh tow twhz data in
FMP1617DAX cmos lpram revision 0.4 jul. 2010 9 low power modes 1. mode register set a19 ~ a5 a4 a3 a2 a1 a0 0 zz enable/disable array on/off on /zz half selection array refresh area /zz enable/disable a4 type 0 deep power down enable 1 dpd disable (default) array on/off on /zz a3 type 0 partial array refresh mode (default) 1 reduced memory size mode note: if the register is written to enable the deep power down, the part will go into deep power down during the following time that /zz is driven low and there is no mrs update. when /zz is driven high, all of the register settings will return to default state for the part (i.e. full array refresh, deep power down disabled). note: the rms(reduced memory size) mode is enabled after /zz goes high and remains enabl ed after /zz goes high. to change to a different mode, the mode register will have to be rewritten. half selection (top / bottom) a2 type 0 bottom (default) 1 top array refresh area a1 a0 type 0 0 full array (default) 01 rfu 10 ?array 11 ?array 2. mrs update address /cs /ub, /lb /we twc twr(4) tbw twp(1) tcw(2) tas(3) taw /zz tzzwe register write start register write complete register update complete the register update take place on the rising edge of /zz. once the register is updat ed, the next time /zz goes low, without an y updates to the register starting within the tzzwe max time of 1us , the part will refresh the arra y selected. the data bus is a don?t care when /zz is low during the register updates.
FMP1617DAX cmos lpram revision 0.4 jul. 2010 10 partial array refresh mode (a3=0, a4=1) reduced memory size mode (a3=1, a4=1) 4. address information parameter description min max units tzzwe zz low to write enable low 0 1 us tr(deep power down mode only) operation recovery time 150 - us tzzmin low power mode time 10 - us a2 a1,a0 refresh section address size density 0 11 1/4 00000h-3ffffh 256kbx16 4mb 0 10 1/2 00000h-7ffffh 512kbx16 8mb x 00 full 00000h-fffffh 1mbx16 16mb 1 11 1/4 c0000h-fffffh 256kbx16 4mb 1 10 1/2 80000h-fffffh 512kbx16 8mb a2 a1,a0 refresh section address size density 0 11 1/4 00000h-3ffffh 256kbx16 4mb 0 10 1/2 00000h-7ffffh 512kbx16 8mb 1 11 1/4 c0000h-fffffh 256kbx16 4mb 1 10 1/2 80000h-fffffh 512kbx16 8mb 3. deep power down mode entry/exit tzzmin tr a4 /cs /ub, /lb /we twc twr(4) tbw twp(1) tcw(2) tas(3) taw /zz tzzwe register write(dpd) deep power down start deep power down exit next cycle
FMP1617DAX cmos lpram revision 0.4 jul. 2010 11 package dimension 48 ball fine pitch bga (0.75mm ball pitch) top view b c #a1 bottom view side view detail a unit : millimeters -mintypmax a - 0.75 - b 5.90 6.00 6.10 b1 - 3.75 - c 7.90 8.00 8.10 c1 - 5.25 - d 0.30 0.35 0.40 e - 1.10 1.20 e1 - 0.85 - e2 0.20 0.25 0.30 y--0.08 d c e2 e e1 0.30 0.85/typ. 0.25/typ. y notes. 1. bump counts : 48(8row x 6column) 2. bump pitch : (x,y)=(0.75 x 0.75)(typ.) 3. all tolerance are +/-0.050 unless otherwise specified. 4. typ : typical 5. y is coplanarity : 0.08(max) b c b/2 b1 0.05 0.05 a1 index mark 6 5 4 3 2 1 a b c d c1/2 c1 e f g h a

▲Up To Search▲

Price & Availability of FMP1617DAX

	To Download FMP1617DAX Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .